The present invention relates to a semiconductor element suited for applications requiring high integration.
An example of a prior art reference showing a single electron memory using polycrystalline silicon disclosed on pp. 541 to 544 by K. Yano et al., IEEE International Electron Devices Meeting, 1993. According to the technique disclosed, the channels for current paths and the memory regions for capturing electrons are simultaneously formed from a polycrystalline silicon thin film. Information is stored by making use of the fact that the threshold voltage changes when electrons are captured in the memory regions. According to this technique, 1 bit is stored corresponding to the storage of one electron. By utilizing the crystal grain of the polycrystalline silicon, a small structure can be realized to operate at room temperature.
In the prior art, a non-volatile memory device such as a flash EEPROM has been realized by using MOSFETs having floating gates and control gates. Information is stored and read out by making use of the fact that the threshold voltage of the MOSFETs is changed by storing carriers in the floating gates. The floating gates are usually made of polycrystalline silicon. By using the MOSFETs with floating gates, the information of 1 bit can be stored for a long time by a single transistor. An example of a prior art structure embodying the memory cell structure of the flash EEPROM is disclosed on pp. 151 to 157 of Nikkei Electronics No. 444, 1988.
Another example of prior art relating to deposition of thin polycrystalline silicon on various insulator films is disclosed by T. Hashimoto et al., Conference on Solid State Devices and Materials, pp 97-100 (1989). Hashimoto et al. disclose that obtaining continuous thin silicon film using LPCVD depositions on CVD SiO2 and on Si3N4 are better than on thermal SiO2.
The present inventors have discovered problems with the prior art structure which has led to the present invention. Some of the problems are first discussed herein.
It is noted that a single electron memory for storing information with a small number of electrons can possibly even operate at a nanometer level because one element can store the information of 1 bit or more and can control the stored charge at one unit. Because of the small number of stored electrons, moreover, drastic improvement can be expected in the rewriting time period and in the rewriting times.
However, the aforementioned single electron memory of the prior art is a single element for storing 1 bit and no means is known for storing the information of 2 bits or more. If this single element is simply used to store the information of N bits (e.g., 65,536 in the case of a 64 Kbit memory), an N number of control electrodes and an N number of current drive paths must be controlled from the outside of the chip. Thus, a 2N number (i.e., 131,072) of terminals are required and this is impractical.
In order to avoid this, the present inventors have found it important to share a terminal among a plurality of memory elements and have made unique investigations to find out the storage of 2 bits with the structure shown in FIG. 3. As shown in FIG. 3, a thin film region (150) lying over an insulator connects first and second low-resistance regions (151) and (152); a thin film region (180) over the insulator connects third and fourth low-resistance regions (181) and (182); and a control electrode (153) covers the first thin film region (150) and the second thin film region (180) partially at a right angle with respect to the first thin film region (150) and the second thin film region (180). This structure reduces the number of the terminals to be driven from the outside, by sharing the control electrode.
However, in this structure, thin film region 1 (150) and thin film region 2 (180) have portions which remain uncovered by the control electrode (153). These portions are too resistive to path a high current, thus leaving a problem that needs to be solved. Moreover, these portions of the thin film region 1 (150) and the thin film region 2 (180), which are not covered by the control electrode (153), may have their potential fluctuated by the capacitive coupling with another electrode or by electromagnetic waves to thereby prevent the stored information from being stably latched.
On the other hand, not only the area occupied by the control electrode, as extended transversely of the drawing, but also the area to be occupied by the thin film polycrystalline silicon or the contacts raise the problem that a large area is necessary for storing 1 bit of information. Moreover, a tolerance is required in order to locate the control electrode (153) correctly over the thin film region 1 (150) or the thin film region 2 (180). This raises another problem due to the restriction that the distance between the low-resistance region 1 (151) and the low-resistance region 2 (152) and the distance between the low-resistance region 3 (181) and the low-resistance region 4 (182) cannot be reduced more than some predetermined values.
Thus, the present inventors have arrived at the present invention based upon these and other previous investigations. Accordingly, it is an object of the present invention to provide a semiconductor memory element which can share terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise.
The present invention provides a structure in which the control electrode entirely covers the thin film regions. With such a structure, the present invention has a low resistance and a strength against external disturbances and also can be manufactured with a small area.
According to a representative mode of practice of the present invention, more specifically, there is provided a semiconductor memory element as shown in FIG. 1. This semiconductor memory element comprises: a thin film region (1) formed over an insulator and made of a semiconductor; first and second low-resistance regions (2) and (3), wherein said thin film region has its one end portion connected with said first low-resistance region (2), and wherein said thin film region has its other end portion connected with said second low-resistance region (3); and a first control electrode (4) for controlling said thin film region, wherein said control electrode (4) covers the entirety of said thin film region.
According to another mode of practice which can reduce the number of terminals of the current drive paths and can be suited for integration, as compared with the case in which single memory elements are simply arranged, there is provided a semiconductor memory element for storing 2 bits or more as shown in FIG. 4. This semiconductor memory element comprises: first and second thin film regions (21) and (22) formed over an insulator and made of a semiconductor; first and second low-resistance regions (23) and (24) are thicker than said thin film regions and formed into a substantially rectangular shape having its longer side two times or more longer than its shorter side, wherein said first thin film region (21) has its one end portion connected with said first low-resistance region (23), wherein said first thin film region (21) has its other end portion connected with said second low-resistance region (24), wherein said second thin film region (22) has its one end portion connected with said first low-resistance region (23), and wherein said second thin film region (22) has its other end portion connected with said second low-resistance region (24); a first control electrode (26) for controlling said first thin film region (21); and a second control electrode (27) for controlling said second thin film region (22).
According to yet another mode of practice which can reduce the number of terminals of the control electrode and can be suited for integration, as compared with the case in which single memory elements are simply arranged, there is provided a semiconductor memory element for storing 2 bits or more as shown in FIG. 6. This semiconductor memory element comprises: first and second thin film regions (143) and (144) formed over an insulator and made of a semiconductor; first, second, third and fourth low-resistance regions (145), (146), (147) and (148) made thicker than said thin film regions, wherein said first thin film region has its one end portion connected with said first low-resistance region (145), wherein said first thin film region has its other end portion connected with said second low-resistance region (146), wherein said second thin film region has its one end portion connected with said third low-resistance region (147), and wherein said second thin film region has its other end portion connected with said fourth low-resistance region (148); and a common control electrode (149) for controlling said first and second thin film regions (143) and (144).
According to a mode of practice which can be controlled with fewer terminals and suited for integration by combining the advantages described above and by arranging the elements in a matrix shape, there is provided a semiconductor memory element for storing 4 bits or more as shown in FIG. 14. This semiconductor memory element comprises: first, second, third and fourth thin film regions (79), (80), (81) and (82) formed over an insulator and made of a semiconductor; first, second, third and fourth low-resistance regions (83), (84), (85) and (86) made thicker than said thin film regions and formed into a substantial rectangle having its longer side longer two times or more longer than its shorter side, wherein said first thin film region (79) has its one end portion connected with said first low-resistance region (83), wherein said first thin film region (79) has its other end portion connected with said second low-resistance region (84), wherein said second thin film region (80) has its one end portion connected with said first low-resistance region (83), wherein said second thin film region (80) has its other end portion connected with said second low-resistance region (84), wherein said third thin film region (81) has its one end portion connected with said third low-resistance region (85), wherein said third thin film region (81) has its other end portion connected with said fourth low-resistance region (86), wherein said fourth thin film region (82) has its one end portion connected with said third low-resistance region (85), and wherein said fourth thin film region (82) has its other end portion connected with said fourth low-resistance region (86); a first control electrode (87) formed into a substantial rectangle having its longer side two times or more longer than its shorter side for controlling said first and third thin film regions (79) and (81); and a second control electrode (88) formed into a substantial rectangle having its longer side two times or more longer than its shorter side for controlling said second and fourth thin film regions (80) and (82).
These and other objects, features and advantages of the present invention will become more apparent in view of the following detailed descriptions of the preferred embodiments.